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RM0008
Note:
23.3.5
Serial peripheral interface (SPI)
communication. The transfer direction (Input/Output) is selected by the BIDIOE bit in the
SPI_CR1 register. When this bit is 1, the data line is output otherwise it is input.
1 clock and 1 data wire (receive-only in full-duplex mode)
In order to free an I/O pin so it can be used for other purposes, it is possible to disable the
SPI output function by setting the RXONLY bit in the SPI_CR1 register. In this case, SPI will
function in Receive-only mode. When the RXONLY bit is reset, the SPI will function in full
duplex mode.
To start the communication in receive-only mode, it is necessary to enable the SPI. In the
master mode, the communication starts immediately and will stop when the SPE bit is reset
and the current reception terminates. In slave mode, the SPI will continue to receive as long
as the NSS is pulled down (or the SSI bit is reset) and the SCK is running.
The SPI can be used in Tx-only mode when the RXONLY bit in the SPI_CR1 register is
reset, the RX pin (MISO in master or MOSI in slave) can be used as GPIO. In this case,
when the data register is read, it does not contain the received value.
In simplex communications, when the SPI master is in Receive-only mode, the clock is
generated continuously once the SPI master has been enabled.
Status flags
Three status flags are provided for the application to completely monitor the state of the SPI
bus.
BUSY flag
This flag indicates the state of the SPI communication layer. When it is set, it indicates that
the SPI is busy communicating and/or there is a valid data byte in the Tx buffer waiting to be
transmitted. The purpose of this flag is to indicate if there is any communication ongoing on
the SPI bus or not. This flag is set as soon as:
1.
2.
Data is written in the SPI_DR register in master mode
The SCK clock is present in slave mode
The BUSY flag is reset each time a byte is transmitted/received. This flag is set and cleared
by hardware. It can be monitored to avoid write collision errors. Writing to this flag has no
effect. The BUSY flag is meaningful only when the SPE bit is set.
Note:
23.3.6
In master receiver mode (1-line bidirectional), the BUSY flag must NOT be checked.
Tx buffer empty flag (TXE)
When it is set, this flag indicates that the Tx buffer is empty and the next data to be
transmitted can be loaded into the buffer. The TXE flag is reset when the Tx buffer already
contains data to be transmitted. This flag is reset when the SPI is disabled (SPE bit is reset).
Rx buffer not empty (RXNE)
When set, this flag indicates that there are valid received data in the Rx Buffer. It is reset
when SPI Data register is read.
CRC calculation
A CRC calculator has been implemented for communication reliability. Separate CRC
calculators are implemented for transmitted data and received data. The CRC is calculated
Doc ID 13902 Rev 9
595/995
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